This invention generally relates to multi-layered semiconductor structures and more particularly to a method for forming a dual damascene structure with improved electrical performance including electromigration resistance and improved metal filling characteristics.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low resistance and capacitance interconnect properties, particularly where submicron inter-layer interconnects and intra-layer interconnects have increasingly high aspect ratios (e.g., an interconnect opening depth to diameter ratio of greater than about 4). In particular, high aspect ratio vias require uniform etching profiles including preventing necking or narrowing of the via opening which detrimentally affects design constraints for electrical resistance in semiconductor device functioning. Such necking or narrowing of the opening can detrimentally affect subsequent processes including adhesion/barrier layer deposition and metal filling deposition frequently resulting in degraded device function including electrical pathway open circuits.
In the fabrication of semiconductor devices, increased device density requires multiple layers, making necessary the provision of a multi-layered interconnect structure. Such a multi-layered interconnect structure typically includes intra-layer conductive interconnects and inter-layer conductive interconnects formed by anisotropically etched openings in an insulating layer, often referred to as inter-metal dielectric (IMD) layers, which are subsequently filled with metal. Commonly used inter-layer high aspect ratio openings are commonly referred to as vias, for example, when the opening extends through an insulating layer between two conductive layers. The intra-layer interconnects extending horizontally in the IMD layer to interconnect different areas within an IMD layer are often referred to as trench lines. In one manufacturing approach, trench lines are formed overlying and encompassing one or more vias to form metal inlaid interconnects referred to as dual damascene structures.
In a typical process for forming multiple layer interconnect structure, for example, a dual damascene process, a first IMD layer is deposited over an etching stop layer overlying a conductive area, for example a metallization layer. A second etching stop layer is formed over the first IMD layer followed by a second IMD layer formed over the second etching stop layer. In one approach to forming a dual damascene structure, via openings are first anisotropically etched through the first and second IMD layers by conventional photolithographic and etching techniques. A second anisotropically etched opening referred to as a trench line is then formed according to a second photolithographic patterning process overlying and encompassing one or more of the via openings. The via openings and the trench line together makeup the dual damascene structure which is subsequently filled with metal, for example, copper, followed by a CMP planarization process to planarize the wafer process surface and prepare the process surface for formation of another overlying layer or level in a multi-layered semiconductor device.
As feature sizes in anisotropic etching process have diminished, photolithographic patterning processes require activating light (radiation) of increasingly smaller wavelength. For 0.25 micron and below CMOS technology, deep ultraviolet (DUV) photoresists have become necessary to achieve the desired resolution. Typically DUV photoresists are activated with activating light source wavelengths of less than about 250 nm, for example, commonly used wavelengths include 193 nm and 248 nm. Many DUV photoresists are chemically amplified using a photoacid generator activated by the light source to make an exposed area soluble in the development process.
One problem affecting DUV photoresist processes is believed to be interference of residual nitrogen-containing species, for example amines, with the DUV photoresist. Residual nitrogen-containing contamination is one of the greater concerns in the use of metal nitride layers such as silicon nitride (e.g., SiN), which are commonly used as an etching stop layer. The silicon nitride layers are frequently formed by CVD processes using amine and amide containing precursors which tend to contaminate the near surface region of IMD layers. Low-k IMD layers, typically having a high degree of porosity, facilitate absorption and transport of contaminating chemical species. For example, it is believed that nitrogen radicals, created during photolithographic patterning due to the presence of nitrogen containing species and absorbed into the IMD layer during metal nitride deposition, interfere with chemically amplified DUV photoresists by neutralizing a photo generated acid catalyst which thereby renders the contaminated-portion of the photoresist insoluble in the developer. As a result, residual photoresist remains on patterned feature edges, sidewalls, or floors of features, detrimentally affecting subsequent anisotropic etching profiles. During anisotropic etching of an overlying feature, for example a trench line opening overlying a via opening, residual photoresist remains or is redeposited on feature opening sidewalls. Consequently, necking, narrowing, or other undesirable etching profiles caused by polymeric residues remaining on feature sidewalls or floors following anisotropic etching, detrimentally affecting subsequent metal filling processes and leading to, for example, electrical open circuits or increased resistivity of interconnect features.
For example, referring to FIG. 1, is shown a dual damascene structure at a stage in manufacturing formed by a typical via-first dual damascene process, where the via opening 20A is first formed followed by forming a trench line opening 20B overlying and encompassing the via opening 20A. The dual damascene structure including the via opening 20A and the trench line opening 20B are formed over an underlying conductive area 12. The dual damascene structure is typically formed by at least two photolithographic patterning and reactive ion etching processes including first forming a via opening 20A followed by a forming the trench line opening 20B including anisotropically etching through a series of layers including for example a bottom anti-reflectance coating (BARC) layer 18; a second dielectric insulating layer 16B; a second etching stop layer 14B; a first dielectric insulating layer 16A; and finally, through a thickness portion of first etching stop layer 14A. The first etching stop layer 14A is subsequently etched through to reveal the underlying conductive area 12.
As previously discussed, a serious problem with prior art processes for forming the dual damascene structure including forming the trench line opening according to an RIE process, is the formation of polymeric residues on feature sidewalls and floors, including what is referred to as a xe2x80x98via fencexe2x80x99 remaining at the trench line bottom portion e.g., 20C, surrounding the via opening 20A. The prior art methods for anisotropic trench etching and dual damascene formation have attempted to achieve substantially vertical sidewall profiles for both the via portion and the trench line portion in an effort to minimize the amount of surface area used by such structures. The presence of an etching stop layer at the trench line/via level helps achieve the goal of substantially vertical via sidewall profiles. One problem with the prior art method for anisotropically etching dual damascene structures including those having an etching stop layer at the trench line/via level is the tendency for polymer deposition around the via opening at the trench line/via level to form via fences detrimentally affecting both resistivity and electro-migration resistance.
There is therefore a need in the semiconductor processing art to develop a method to reliably anisotropically etch dual damascene structures to avoid via fences and having improved electrical performance.
It is therefore an object of the invention to provide a method to reliably anisotropically etch dual damascene structures to avoid via fences and having improved electrical performance while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for selectively anisotropically a semiconductor feature to form a tapered sidewall profile.
In a first embodiment, the method includes providing a semiconductor wafer including an anisotropically etched feature formed in at least one dielectric insulating layer including a relatively larger width dimension portion overlying and encompassing at least one relatively smaller diameter dimension portion the smaller diameter dimension portion further including a bottom portion including an overlying liner; and, selectively anisotropically etching the anisotropically etched feature according to a reactive ion etching (RIE) process to form a tapered sidewall portion of the at least one relatively smaller diameter portion.
These and other embodiments, aspects and features of the invention will become better understood from a detailed description of the preferred embodiments of the invention which are described in conjunction with the accompanying drawings.